EDN

Energy-Saving Flip-Flop Circuit

Toshiba Corporation today announced that it has developed a new flip-flop circuit using 40nm CMOS process that will reduce power consumption in mobile equipment. Measured data verifies that the power ...
Semiconductor Engineering

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node

Researchers present 3 DICE IFF designs with transistor interleaving, the CnRx construct, and the guard gate technique at the 22 nm FD SOI technology node. April 25th, 2022 - By: Technical Paper Link ...
Electronics Weekly

Toshiba develops power-saving flip-flop

Toshiba has developed a new flip-flop circuit using 40nm CMOS process that will reduce power consumption in mobile equipment. Measured data verifies that the power dissipation of the new flip-flop is ...
Design-Reuse

High Density - Low power Flip-Flop

Gaurav Goyal, Reecha Jajodia, Shahab Akhtar; Freescale Semiconductor India Pvt. Ltd. In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the ...
EDN

In Circuit Transistor Checker

This simple circuit has helped me out on many occasions. It is able to check transistors, in the circuit, down to 40 ohms across the collector-base or base-emitter junctions. It can also check the ...